The present invention relates to a two step variable length delay circuit, in particular, which is used for a delay-locked loop (DLL) in a clock generating circuit of an information processing apparatus and in a timing generating circuit of a communication processing apparatus.
As a first conventional example, a technical report, xe2x80x9cA Semidigital Dual Delay-Locked Loopxe2x80x9d written by S. Sidiropoulos et al., has been reported in IEEE Journal of Solid-State Circuits, vol. 32, pp. 1683-1692, November 1997. And as a second conventional example, Japanese Patent Application Laid-Open No. HEI 11-261408 discloses xe2x80x9cPhase Interpolator, Timing Signal Generating Circuit, and Semiconductor Integrated Circuit and Semiconductor Integrated Circuit System Applied This Timing Signal Generating Circuit.xe2x80x9d In these conventional examples, a variable length delay circuit is realized by an analog mixer circuit that mixes currents of two signals whose phases are different each other, however, it is difficult to realize its required specifications due to the dispersion of the circuits. Therefore, a variable length delay circuit, in which its easy designing and operation stability are secured by using digital circuits, has been required.
As a third conventional example, a technical report, xe2x80x9cA Portable Digital DLL Architecture for CMOS Interface Circuitsxe2x80x9d written by Bruno W. Garlepp et al., has been reported in 1998 Symposium on VLSI Circuits Digest of Technical Papers, pp. 214-215. In this conventional example, in order to meet the request mentioned above, not only a controlling circuit but also delay elements are digitized.
FIG. 1 is a circuit diagram showing a two step variable length delay circuit including interpolators at the third conventional example. Referring to FIG. 1, the two step variable length delay circuit at the third conventional example is explained.
The two step variable length delay circuit at the third conventional example provides inputs In1 and In2, outputs a to c and e to i, buffers (inverters) B100 to B103, B121 to B123, B123i, B200 to B203, and B213i, and interpolators ip120, ip121, and ip122.
The interpolator ip120 provides buffers B120 and B210, the interpolator ip121 provides buffers B120i and B121i, and the interpolator ip122 provides buffers B210i and B211i. 
In this, an output from the inverter B100, to which the input In1 is inputted, is amplified by the buffer B101 and the output a is outputted, and an output from the inverter B200, to which the input In2 is inputted, is amplified by the buffer B201 and the output c is outputted. The interpolator ip120 mixes currents of the outputs from the buffers B120 and B210 by connecting them, and the output from the interpolator ip120 is amplified at the buffer B121 and the output b is outputted. And the phase of the output b becomes the middle phase of the outputs a and c in this digital circuit of the two step variable length delay circuit at the third conventional example.
Further, the output a from the buffer B101 is inputted to the inverter B102, and the buffer B103 amplifies the output from the inverter B102. The output b from the buffer B121 is inputted to the inverter B122, and the buffer B123 amplifies the output from the inverter B122. The interpolator ip121 outputs a signal by connecting the output from the B120i, to which the output a is inputted, and the output from the B121i, to which the output b is inputted, and the buffer B123i amplifies the output from the interpolator ip121. The interpolator ip122 outputs a signal by connecting the output from the B210i, to which the output b is inputted, and the output from the B211i, to which the output c is inputted, and the buffer B213i amplifies the output from the interpolator ip122. The output c from the buffer B201 is inputted to the inverter B202, and the buffer B203 amplifies the output from the inverter B202. With this structure, fine time intervals are obtained.
At the third conventional example, as mentioned above, three interpolators are used and the eight outputs are obtained by dividing the input phases into eight. In this, actually, nine outputs are obtained, but the ninth output is not outputted, because the ninth output is equal to the first output at the next output combination.
As a fourth conventional example, Japanese Patent Application Laid-Open No. 2000-163961 discloses xe2x80x9cSynchronous Type Semiconductor IC.xe2x80x9d In this application, an internal clock signal being synchronized with an external clock signal is generated by applying a fine adjustment to phases, after a coarse adjustment was applied to the phases. With this, generating a glitch caused by the change of the input signal is prevented.
As a fifth conventional example, Japanese Patent Application Laid-Open No. 2000-195166 discloses xe2x80x9cDelay Time Control Circuit.xe2x80x9d In this application, pulse signals delayed by a designated delay time are counted by using a delay circuit, and pulse signals having a suitable delay time are generated, even when the delay time of a unit circuit is changed.
As a sixth conventional example, Japanese Patent Application Laid-Open No. 2000-252802 discloses xe2x80x9cClock Cycle Detecting Circuit.xe2x80x9d In this application, an operating range of the phase adjustment is widened by applying the coarse adjustment beforehand.
As a seventh conventional example, Japanese Patent Application Laid-Open No. 2000-298532 discloses xe2x80x9cTiming Control Circuit.xe2x80x9d In this application, the timing control circuit provides a coarse timing control circuit that coarsely adjusts the phase difference between an input clock signal and an output clock signal, and a fine timing control circuit that finely adjusts the phase difference in case that the delay time is change caused by like a temperature rise.
And as an eighth conventional example, Japanese Patent Application Laid-Open No. HEI 6-204792 discloses xe2x80x9cDelay Circuit.xe2x80x9d In this application, the delay circuit provides a coarse adjusting section and a fine adjusting section, and adjusts the amount of delay by using a wide variable range and a fine minimum step.
At the third conventional example shown in FIG. 1, in order to form a middle phase at an interpolator, the sizes (on resistance values) of transistors are decided in the following. That is, the size of the transistors of the two step inverters B100 and B101, which generate the outputs a, is 10, and also the size of the transistors of the two step inverters B200 and B201, which generate the outputs c, is 10. And the size of transistor of the inverter B120 connecting to the input In1 whose phase is lead is set to be 6, and the size of transistor of the inverter B210 connecting to the input In2 whose phase is lag is set to be 4. And by connecting the outputs from the B120 and B210, the output b having the middle phase between the outputs a and c is obtained by mixing through the inverter B121 formed by the size of transistor being 10.
At this time, a phase lead signal in the two signals is inputted to the input In1, and even when the inverter B120, whose output is connected to the output of the inverter B210, changes, the inverter B210, to which a phase lag signal is inputted, stays unchanged. And since both a p channel transistor of the B120 and an n channel transistor of the B210 become xe2x80x9conxe2x80x9d, the output becomes a voltage divided value by the on resistance of the both transistors. Consequently, the phase lead input signal is delayed more than the value outputting from the two step inverters B100 and B101, and when the phase lag signal is inputted to the In2 and the B210 changes, the phase lead signal is changed immediately. Therefore, the phase lead signal changes faster than that the phase lag signal is outputted from the two step inverters B200 and B201. With this, a middle phase signal output can be obtained.
However, when the phase lead signal is inputted to the input In1, which is connected to the inverter B120 whose output is connected to the output of the inverter B210, that is, the both outputs are connected, the output load is heavy and the output is liable to be delayed. Therefore, in order to obtain the middle phase, the size of the transistor of the B120 is made to be larger than that of the B210 connecting the In2 for the phase lag signal input. Consequently, there is a limitation that the phase lead signal is always inputted to the input In1 for the phase lead signal input, in order to obtain the middle phase signal.
FIG. 2 is a block diagram showing the two step variable length delay circuit at the third conventional example. Referring to FIG. 2, a structure and an operation of the two step variable length delay circuit at the third conventional example are explained. Especially, the limitation mentioned above at the operation is explained.
As shown in FIG. 2, the two step variable length delay circuit at the third conventional example consists of a delay chain 601, a delay chain 602, a phase splitter 603, an end-of-cycle detector 604, a counter and control logic and selection logic 605, a 32:1 multiplexer 606, a three stage interpolator 607, a 16:1 multiplexer 608, a filter 609, and a phase detector 610.
As mentioned above, at the third conventional example, there is the limitation that the phase lead signal is always inputted to the input In1 for the phase lead signal input. Therefore, since the total number of taps of the delay chains 601 and 602 is 32, in order to make the number of inputs 32 be equal to two outputs, the 32:1 multiplexer 606 is required for the In1 for phase lead signal input and the In2 for phase lag signal input.
Under this structure, even when signals are extracted from the same tap, the routes where the signals are transmitted are different. Therefore, dispersion between the delay time from the input In1 for phase lead signal input to the output of the phase lead signal and the delay time from the input In2 for phase lag signal input to the output of the phase lag signal occurs. And the delay time of them does not become the same. That is, even when the same input is inputted to the inputs In1 and In2, there is a defect that the same delay time cannot be obtained. Consequently, when the tap outputs of the delay chains 601 and 602 are switched, there is a problem that a uniform time interval cannot be generated.
Further, wedge shaped pulses are generated at the delays at the 32:1 multiplexer 606 and the 3 stage interpolator 607. In order to solve this problem, it is necessary that both the inputs in1 and In2 are switched at the level 0, however, there is a problem that generating this timing is difficult.
At the fourth conventional example, as mentioned above, after the coarse adjustment was applied to the phase, the fine adjustment is applied to the phase. When a coarse adjusting tap is changed, a change of a coarse adjustment 1 tap is generated in the output, therefore there is a defect that the jitters of the output become large at an DLL that always adjusts. And the length of the fine adjustment is decided as the length of the 1 tap coarse adjustment, however, it cannot be executed that the fine adjustment range is made to be equal to the coarse adjustment 1 tape, by the dispersion. Even when the fine adjustment and the coarse adjustment are executed at the same time, there are problems that the phase changes of the equal interval cannot be realized and setting the switching timing is difficult.
At the fifth conventional example, the example does not have a structure in which the delay time is adjusted finely in wide range, and it is impossible to meet immediately a request in which the delay time is adjusted in a finer time interval. Further, it is impossible to constrain pulse shaped noise generated at the time when the unit delay circuit is switched.
At the sixth conventional example, the delay circuit is an analog circuit and it is difficult to design the circuit. When a coarse adjusting tap is changed, a change of a coarse adjustment 1 tap is generated in the output, therefore there is a defect that the jitters of the output become large at an DLL that always adjusts. And the length of the fine adjustment is decided as the length of the 1 tap coarse adjustment, however, it cannot be executed that the fine adjustment range is made to be equal to the coarse adjustment 1 tap, by the dispersion. Even when the fine adjustment and the coarse adjustment are executed at the same time, there are problems that the phase changes of the equal interval cannot be realized and setting the switching timing is difficult.
At the seventh conventional example, the delay circuit is an analog circuit and it is difficult to design the circuit. When a coarse adjusting tap is changed, a change of a coarse adjustment 1 tap is generated in the output, therefore there is a defect that the jitters of the output become large at an DLL that always adjusts.
And at the eighth conventional example, analog circuits are used and it is difficult to design the circuits. And the length of the fine adjustment is decided as the length of the 1 tap coarse adjustment, and the fine adjustment range is made to be equal to the coarse adjustment 1 tape, however, it is difficult to constrain pulse shaped noise generated at the time when the coarse adjusting section is switched, by the dispersion.
It is therefore an object of the present invention to provide a two step variable length, delay circuit, in which digital elements being able to make delay time variable easily are used, and its phase adjusting range is wide and can adjust the phase finely, and better jitter performance is realized, and pulse shaped noise (glitches) is prevented.
According to a first aspect of the present invention, there is provided a two step variable length delay circuit. At the two step variable length delay circuit, an input signal is delayed by a designated time interval every time when the input signal is passed through one of delay elements and plural delayed signals are generated, and m pieces of the plural delayed signals are selected and the selected m pieces of the plural delayed signals are made to be the first to the mth coarse adjustment delay signals (m is an integer being 3 or more), and the nth coarse adjustment delay signal has a more lead phase by a time interval dtc than the (n+1)th coarse adjustment delay signal has (n is an integer being 1 or more and (mxe2x88x921) or less), and 2m pieces of fine adjustment delay signals are generated, based on signals, which the first to the mth coarse adjustment delay signal are amplified, and signals that waveforms of the nth and the (n+1)th coarse adjustment delay signals are mixed, and a signal that waveforms of the mth and the first coarse adjustment delay signals are mixed, and the jth fine adjustment delay signal has a more lead phase by a time interval dtcxe2x80x2, being finer than the time interval dtc, than the (j+1)th fine adjustment delay signal has (j is an integer being 1 or more and (2mxe2x88x922) or less), excluding a time interval between a fine adjustment delay signal generated from the mth and first coarse adjustment delay signals and the other fine adjustment delay signals, and in case that one of the 2m pieces of fine adjustment delay signals is selecting at present, and when the selecting fine adjustment delay signal is switched, one of the coarse adjustment delay signals excluding the coarse adjustment delay signal(s) using for generating selecting the fine adjustment delay signal is selected as the coarse adjustment delay signal to be switched.
According to a second aspect of the present invention, in the first aspect, the coarse adjustment delay signal to be switched is a coarse adjustment delay signal whose phase difference is the largest in coarse adjustment delay signal(s) from the coarse adjustment delay signal(s) using at the time when the fine adjustment delay signal, which is being selected at the time of switching, is generated, and further, a coarse adjustment delay signal, which is switched, in case that the phase difference between a fine adjustment delay signal that a coarse adjustment delay signal after switched is amplified and a fine adjustment delay signal that is selected after switching is smaller than the phase difference between the fine adjustment delay signal that the coarse adjustment delay signal to be switched is amplified and the fine adjustment delay signal that is being selected at the time of switching.
According to a third aspect of the present invention, in the first aspect, in case that the being selected fine adjustment delay signal is switched to a fine adjustment delay signal whose phase is more lead by the time interval dtcxe2x80x2 than the phase of the being selected fine adjustment delay signal, as the coarse adjustment delay signal to be switched, a delayed input signal, whose phase is more lead by the time interval (mxc3x97dtc) than the phase of the coarse adjustment delay signal to be switched, is selected. And in case that the being selected fine adjustment delay signal is switched to a fine adjustment delay signal whose phase is more lag by the time interval dtcxe2x80x2 than the phase of the being selected fine adjustment delay signal, as the coarse adjustment delay signal to be switched, a delayed input signal, whose phase is more lag by the time interval (mxc3x97dtc) than the phase of the coarse adjustment delay signal to be switched, is selected.
According to a fourth aspect of the present invention, there is provided a two step variable length delay circuit. The two step variable length delay circuit provides a delay means, in which three or more delay elements having delay time of a time interval of dtc are connected in series, and which outputs each output from the delay elements, whose phase is delayed by the time interval dtc from the phase of an output of a delay element of a previous stage, as that the side to which an input signal is inputted is made to be the previous stage, a first selection means that selects the outputs of m pieces of the delay elements from the outputs of the delay elements (m is an integer being 3 or more), a waveform mixing means RIa, which outputs the first to the (2mxe2x88x921)th signal outputs that the outputs of the m pieces delay elements are amplified, and outputs each signal, whose phase is middle between the nth (n is an integer being 1 or more and (mxe2x88x921) or less) input and the (n+1)th input, is generated by that waveforms of the nth input and the (n+1)th input, whose phase difference between them is the time difference dtc, are mixed, and also outputs a signal, whose phase is middle between the first input and the mth input, is generated by that waveforms of the first input and the mth input are mixed, and a second selection means that selects one of the outputs from the waveform mixing means RIa. And when the output from the waveform mixing means RIa, being selected by the second selection means, is switched to another output, an output from one of the delay elements, which is not used at the time when the being selected output from the waveform mixing means RIa is generated, is used as another output.
According to a fifth aspect of the present invention, in the fourth aspect, at the waveform mixing means RIa, an output amplified the phase of the nth input is made to be the (2nxe2x88x921)th output, an output amplified the phase of the mth input is made to be the (2mxe2x88x921)th output, an output that the waveforms of the nth input and the (n+1)th input are mixed is made to be the 2nth output, an output that the waveforms of the mth input and the first input are mixed is made to be the 2mth output, and the phase difference between the jth output (j is an integer being 1 or more and (2mxe2x88x922) or less) and the (j+1)th output is (dtc/2). And when an output from the delay elements is selected so that an input whose phase is more lead by the time interval dtc is inputted to the mth input than the phase of the first input, the phase difference between the (2mxe2x88x921)th output and the 2mth output becomes the time interval (dtc/2).
According to a sixth aspect of the present invention, in the fourth aspect, the waveform mixing means RIa is a ring interpolator RIa. And the ring interpolator RIa provides m pieces of buffers that amplify each of the inputs from the first to the mth inputs, (mxe2x88x921) pieces of interpolators IPx (x is an integer being 1 or more and (mxe2x88x921) or less), and the mth interpolator IPm. And at each of the (mxe2x88x921) pieces of the interpolators IPx, the nth input is inputted to its phase lead input and the (n+1)th input is inputted to its phase lag input, and each of the (mxe2x88x921) pieces of the interpolators IPx amplifies the nth input and the (n+1)th input and connects both the amplified inputs and generates an output whose phase is middle between the phases of the nth and the (n+1)th inputs by mixing waveforms of both the inputs. And at the mth interpolator IPm, in which the mth input is inputted to its phase lead input and the first input is inputted to its phase lag input, the interpolators IPm amplifies the mth input and the first input and connects both the amplified inputs and generates an output whose phase is middle between the phases of the mth and the first inputs by mixing waveforms of both the inputs.
According to a seventh aspect of the present invention, in the fourth aspect, each of the delay elements is a digital circuit that has delay time of the time interval dtc.
According to an eighth aspect of the present invention, in the fourth aspect, the two step variable length delay circuit further provides a first control means that sends a first selection signal, which makes the first selection means select the m pieces of outputs of delay elements from the outputs of the delay elements, and a second control means that sends a second selection signal, which makes the second selection means select the one piece of outputs of the waveform mixing means RIa from the outputs of the waveform mixing means RIa.
According to a ninth aspect of the present invention, in the eighth aspect, when the first control means receives a first delaying signal that makes the output from the waveform mixing means RIa being selected by the second selection means switch to an output having more phase lead of the waveform mixing means RIa, the first control means makes an output of the delay element that is not using at the time when the waveform mixing means RIa is generating the selected output be an output from the delay element to be switched, and the first control means makes the first selection means switch to an output from the delay element whose phase is lead by the time interval (mxc3x97dtc), and controls the first selection means so that the first selection means selects m pieces of sequential outputs from the delay elements.
According to a tenth aspect of the present invention, in the ninth aspect, the output from the delay element to be switched, when the first delaying signal was received, is, an output from the delay element whose phase difference is the largest from the outputs of the delay elements using at the time when the output from the waveform mixing means RIa is generated, which is being selected at the time of switching by the second selection means, and further, an output from the delay element that is switched, in case that the phase difference between an output from the waveform mixing means RIa that an output of a delay element after switching is amplified and an output from the waveform mixing means RIa selecting after switched is smaller than the phase difference between an output from the waveform mixing means RIa that the output of the delay element to be switched is amplified and the output from the waveform mixing means RIa that are being selected at the time of switching.
According to an eleventh aspect of the present invention, in the ninth aspect, in case that the pth output (p is an integer being 2 or more and 2m or less) from the waveform mixing means RIa is being selected by the second selection means, and the second control means received the first delaying signal, the second control means controls the second selection means so that the second selection means switches the pth output from the waveform mixing means RIa to the (pxe2x88x921)th output from the waveform mixing means RIa. And in case that the first output from the waveform mixing means RIa is being selected by the second selection means, and the second control means received the first delaying signal, the second control means controls the second selection means so that the second selection means switches the first output from the waveform mixing means RIa to the 2mth output from the waveform mixing means RIa.
According to a twelfth aspect of the present invention, in the eighth aspect, when the first control means receives a first advancing signal that makes the output from the waveform mixing means RIa being selected by the second selection means switch to an output having more phase lag of the waveform mixing means RIa, the first control means makes an output of the delay element that is not using at the time when the waveform mixing means RIa is generating the selected output be an output from the delay element to be switched, and the first control means makes the first selection means switch to an output from the delay element whose phase is lag by the time interval (mxc3x97dtc), and controls the first selection means so that the first selection means selects m pieces of sequential outputs from the delay elements.
According to a thirteenth aspect of the present invention, in the twelfth aspect, the output from the delay element to be switched, when the first advancing signal was received, is, an output from the delay element whose phase difference is the largest from the outputs of the delay elements using at the time when the output from the waveform mixing means RIa is generated, which is being selected at the time of switching by the second selection means, and further, an output from the delay element that is switched, in case that the phase difference between an output from the waveform mixing means RIa that an output of a delay element after switching is amplified and an output from the waveform mixing means RIa selecting after switched is smaller than the phase difference between an output from the waveform mixing means RIa that the output of the delay element to be switched is amplified and the output from the waveform mixing means RIa that are being selected at the time of switching.
According to a fourteenth aspect of the present invention, in the twelfth aspect, in case that the qth output (q is an integer being 1 or more and (2mxe2x88x921) or less) from the waveform mixing means RIa is being selected by the second selection means, and the second control means received the first advancing signal, the second control means controls the second selection means so that the second selection means switches the qth output from the waveform mixing means RIa to the (q+1)th output from the waveform mixing means RIa. And in case that the 2mth output from the waveform mixing means RIa is being selected by the second selection means, and the second control means received the first advancing signal, the second control means controls the second selection means so that the second selection means switches the 2mth output from the waveform mixing means RIa to the first output from the waveform mixing means RIa.
According to a fifteenth aspect of the present invention, in the fourth aspect, the two step variable length delay circuit further provides r pieces of waveform mixing means (r is an integer being 1 or more), which are connected in series and disposed between the waveform mixing means RIa and the second selection means.
According to a sixteenth aspect of the present invention, in the fifteenth aspect, in case that the output side of the waveform mixing means RIa, to which one of the r pieces of the waveform mixing means is connected, is defined as a previous stage, and the input side of the second selection means is defined as a next stage, at the sth (s is an integer being 1 or more and r or less) waveform mixing means in the r pieces of the waveform mixing means, by counting from the previous stage. And in case that the outputs of the m delay elements, selected by the first selection means, are inputted to the first to the mth input of the waveform mixing means RIa in phase lead order, the first to the (mxc3x972S) outputs from the previous waveform mixing means are inputted to the first to the (mxc3x972S) inputs of the sth waveform mixing means respectively, and the outputs, which the first to the (mxc3x972S+1xe2x88x921) outputs were amplified, are made to be the first to the (mxc3x972S) inputs, and the output, which waveforms of the tth input (t is an integer being 1 or more and (mxc3x972Sxe2x88x921) or less) and the (t+1)th input are mixed, is made to be the 2tth output, and the output, which waveforms of the (mxc3x972S)th input and the first input are mixed, is made to be the (mxc3x972S+1) output. And in case that the time interval between the nth input (n is an integer being 1 or more and (mxe2x88x921) or less) and the (n+1)th input being the outputs from the m delay elements selected by the first selection means is (dtc), the phase difference between the tth input and the (t+1)th input is the time interval (dtc/2S) in the range that the t is 1 to (2Sxc3x97(mxe2x88x921)+1), and the phase difference between the uth output and the (u+1)th output is the time interval (dtc/2S+1) in the range that the u is 1 to (2S+1xc3x97(mxe2x88x921)+1). And when the phase of the mth input being the output from the mth delay element selected by the first selection means becomes more lead than the phase of the first input, the phase difference between the tth input and the (t+1)th input is the time interval (dtc/2S) in the range that the t is (2Sxc3x97(mxe2x88x921)+1) to (mxc3x972S), and the phase difference between the uth output and the (u+1)th output is the time interval (dtc/2S+1) in the range that the u is (2S+1xc3x97(mxe2x88x921)+1) to (mxc3x972S+1).
According to a seventeenth aspect of the present invention, in the sixteenth aspect, the sth waveform mixing means in the r pieces of the waveform mixing means is a ring interpolator. And the sth waveform mixing means provides (mxc3x972S) pieces of buffers that amplify each of the inputs from the first to the (mxc3x972S)th, (mxc3x972Sxe2x88x921) pieces of interpolators ipy (y is an integer being 1 or more and (mxc3x972Sxe2x88x921) or less), and an interpolator ip (mxc3x972S). And at each of the (mxc3x972Sxe2x88x921) pieces of interpolators ipy, the tth input is inputted to its phase lead input and the (t+1)th input is inputted to its phase lag input, and each of the (mxc3x972Sxe2x88x921) pieces of interpolators ipy amplifies the tth input and the (t+1)th input and connects both the amplified outputs and generates an output whose phase is middle between the phases of the tth and the (t+1)th inputs by mixing waveforms of both the outputs. And at the interpolator ip (mxc3x972S), in which the (mxc3x972S)th input is inputted to its phase lead input and the first input is inputted to its phase lag input, and the interpolator ip (mxc3x972S) amplifies the (mxc3x972S)th input and the first input and connects both the amplified outputs and generates an output whose phase is middle between the phases of the (mxc3x972S)th and the first inputs by mixing waveforms of both the outputs.
According to an eighteenth aspect of the present invention, in the fifteenth aspect, the second selection means selects one of the outputs from the last waveform mixing means in the r pieces of the waveform mixing means connecting to the second selection means, in case that the r pieces of waveform mixing means, which are connected in series, are disposed between the waveform mixing means RIa and the second selection means.
According to a nineteenth aspect of the present invention, in the eighteenth aspect, when the first control means receives a second delaying signal that makes the output from the last waveform mixing means being selected by the second selection means switch to an output having more phase lead of the last waveform mixing means, the first control means makes an output of the delay element that is not using at the time when the last waveform mixing means is generating the selected output be an output from the delay element to be switched, and the first control means makes the first selection means switch to an output from the delay element whose phase is lead by the time interval (mxc3x97dtc), and controls the first selection means so that the first selection means selects m pieces of sequential outputs from the delay elements.
According to a twentieth aspect of the present invention, in the nineteenth aspect, the output from the delay element to be switched, when the second delaying signal was received, is, an output from the delay element whose phase difference is the largest from the outputs of the delay elements using at the time when the output from the last waveform mixing means is generated, which is being selected at the time of switching by the second selection means, and further, an output from the delay element that is switched, in case that the phase difference between an output from the last waveform mixing means that an output of a delay element after switching is amplified and an output from the last waveform mixing means selecting after switched is smaller than the phase difference between an output from the last waveform mixing means that the output of the delay element to be switched is amplified and the output from the last waveform mixing means that are being selected at the time of switching.
According to a twenty-first aspect of the present invention, in the nineteenth aspect, in case that the fth output (f is an integer being 2 or more and (mxc3x972S+1)or less) from the last waveform mixing means is being selected by the second selection means, and the second control means received the second delaying signal, the second control means controls the second selection means so that the second selection means switches the fth output from the last waveform mixing means to the (fxe2x88x921)th output from the last waveform mixing means.
According to a twenty-second aspect of the present invention, in the nineteenth aspect, in case that the first output from the last waveform mixing means is being selected by the second selection means, and the second control means received the second delaying signal, the second control means controls the second selection means so that the second selection means switches the first output from the last waveform mixing means to the (mxc3x972S+1)th output from the last waveform mixing means.
According to a twenty-third aspect of the present invention, in the eighteenth aspect, when the first control means receives a second advancing signal that makes the output from the last waveform mixing means being selected by the second selection means switch to an output having more phase lag of the last waveform mixing means, the first control means makes an output of the delay element that is not using at the time when the last waveform mixing means is generating the selected output be an output from the delay element to be switched, and the first control means makes the first selection means switch to an output from the delay element whose phase is lag by the time interval (mxc3x97dtc), and controls the first selection means so that the first selection means selects m pieces of sequential outputs from the delay elements.
According to a twenty-fourth aspect of the present invention, in the twenty-third aspect, the output from the delay element to be switched, when the second advancing signal was received, is, an output from the delay element whose phase difference is the largest from the outputs of the delay elements using at the time when the output from the last waveform mixing means is generated, which is being selected at the time of switching by the second selection means, and further, an output from the delay element that is switched, in case that the phase difference between an output from the last waveform mixing means that an output of a delay element after switching is amplified and an output from the last waveform mixing means selecting after switched is smaller than the phase difference between an output from the last waveform mixing means that the output of the delay element to be switched is amplified and the output from the last waveform mixing means that are being selected at the time of switching.
According to a twenty-fifth aspect of the present invention, in the twenty-third aspect, in case that the gth output (g is an integer being 1 or more and (mxc3x972S+1xe2x88x921) or less) from the last waveform mixing means is being selected by the second selection means, and the second control means received the second advancing signal, the second control means controls the second selection means so that the second selection means switches the gth output from the last waveform mixing means to the (g+1)th output from the last waveform mixing means.
According to a twenty-sixth aspect of the present invention, in the twenty-third aspect, in case that the (mxc3x972S+1)th output from the last waveform mixing means is being selected by the second selection means, and the second control means received the second advancing signal, the second control means controls the second selection means so that the second selection means switches the (mxc3x972S+1)th output from the last waveform mixing means to the first output from the last waveform mixing means.
According to a twenty-seventh aspect of the present invention, in the sixth aspect, when two signals whose phases are different each other are inputted to the ring interpolator RIa, and in case that a phase lead signal is inputted to a buffer B3 and a phase lag signal is inputted to a buffer B4, and the interpolator IPx and the interpolator IPm provide a buffer B1 to which the phase lead signal is inputted and a buffer B2 to which the phase lag signal is inputted, on resistance values of transistors of the buffers B1 and B2 are decided so that the phase of the output, which the outputs from the buffers B1 and B2 are connected and their waveforms are mixed, becomes the middle phase between the phase of the output from the buffer B3, the phase lead signal was amplified, and the phase of the output from the buffer B4, the phase lag signal was amplified.
According to a twenty-eighth aspect of the present invention, in the seventeenth aspect, when two signals whose phases are different each other are inputted to the ring interpolator, and in case that a phase lead signal is inputted to a buffer B3 and a phase lag signal is inputted to a buffer B4, and the interpolator ipy and the interpolator ip (mxc3x972S) provide a buffer B1 to which the phase lead signal is inputted and a buffer B2 to which the phase lag signal is inputted, on resistance values of transistors of the buffers B1 and B2 are decided so that the phase of the output, which the outputs from the buffers B1 and B2 are connected and their waveforms are mixed, becomes the middle phase between the phase of the output from the buffer B3, the phase lead signal was amplified, and the phase of the output from the buffer B4, the phase lag signal was amplified.
According to a twenty-ninth aspect of the present invention, in the twenty-seventh and the twenty-eighth aspects, each of the buffers B1, B2, B3, and B4 is an amplifier or an inverter.